Skip to product information
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
  • The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

$125.99 $139.99

Reliable shipping

Flexible returns

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

Jespers, Paul

In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com  allow redoing the tests.

Details

Published by: Springer

Publication Date: 2009-12-04

Format: Hardcover

ISBN-13: 9780387471006

DOI: 10.1007/978-0-387-47101-3

Dimensions: 235.0cm x155.0cm

Pages: 171.0

You may also like