{"product_id":"9780792393153","title":"IDDQ Testing of VLSI Circuits","description":"\u003ch1\u003eIDDQ Testing of VLSI Circuits\u003c\/h1\u003e \u003ch2\u003eGulati, Ravi K.; Hawkins, Charles F.\u003c\/h2\u003e \u003cp\u003ePower supply current monitoring to detect CMOS IC defects  during production testing quietly laid down its roots in the  mid-1970s. Both Sandia Labs and RCA in the United States and Philips  Labs in the Netherlands practiced this procedure on their CMOS ICs. At  that time, this practice stemmed simply from an intuitive sense that  CMOS ICs showing abnormal quiescent power supply current (I\u003csub\u003eDDQ\u003c\/sub\u003e)  contained defects. Later, this intuition was supported by data and  analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton),  Soden and Hawkins (Sandia Labs and the University of New Mexico),  Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and  Maly and co-workers (Carnegie Mellon University).  Interest in I\u003csub\u003eDDQ\u003c\/sub\u003e testing has advanced beyond the data reported  in the 1980s and is now focused on applications and evaluations  involving larger volumes of ICs that improve quality beyond what can  be achieved by previous conventional means.  In the conventional style of testing one attempts to propagate the  logic states of the suspended nodes to primary outputs. This is done  for all or most nodes of the circuit. For sequential circuits, in  particular, the complexity of finding suitable tests is very high. In  comparison, the I\u003csub\u003eDDQ\u003c\/sub\u003e test does not observe the logic states,  but measures the integrated current that leaks through all gates. In  other words, it is like measuring a patient's temperature to determine  the state of health.  Despite perceived advantages, during the years that followed its  initial announcements, skepticism about the practicality of  I\u003csub\u003eDDQ\u003c\/sub\u003e testing prevailed. The idea, however, provided a great  opportunity to researchers. New results on test generation, fault  simulation, design for testability, built-in self-test, and diagnosis  for this style of testing have since been reported. After a decade of  research, we are definitely closer to practice.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 1992-12-31\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9780792393153\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4615-3146-3\u003c\/p\u003e \u003cp\u003eDimensions: 254cm x178cm\u003c\/p\u003e \u003cp\u003ePages: 124\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":47185241997452,"sku":"9780792393153","price":98.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9780792393153.jpg?v=1775012743","url":"https:\/\/lateknightbooks.com\/products\/9780792393153","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}