{"product_id":"9780792395058","title":"Modeling of Electrical Overstress in Integrated Circuits","description":"\u003ch1\u003eModeling of Electrical Overstress in Integrated Circuits\u003c\/h1\u003e \u003ch2\u003eDiaz, Carlos H.; Sung-Mo (Steve) Kang; Duvvury, Charvaka\u003c\/h2\u003e \u003cp\u003eElectrical overstress (EOS) and Electrostatic discharge (ESD)  pose one of the most dominant threats to integrated circuits (ICs).  These reliability concerns are becoming more serious with the downward  scaling of device feature sizes.  \u003cem\u003eModeling of Electrical Overstress  in\u003c\/em\u003e \u003cem\u003eIntegrated Circuits\u003c\/em\u003e presents a comprehensive analysis of  EOS\/ESD-related failures in I\/O protection devices in integrated  circuits. \u003cbr\u003e  The design of I\/O protection circuits has been done in a hit-or-miss  way due to the lack of systematic analysis tools and concrete design  guidelines. In general, the development of on-chip protection  structures is a lengthy expensive iterative process that involves  tester design, fabrication, testing and redesign. When the technology  is changed, the same process has to be repeated almost entirely. This  can be attributed to the lack of efficient CAD tools capable of  simulating the device behavior up to the onset of failure which is a  3-D electrothermal problem. For these reasons, it is important to  develop and use an adequate measure of the EOS robustness of  integrated circuits in order to address the on-chip EOS protection  issue. Fundamental understanding of the physical phenomena leading to  device failures under ESD\/EOS events is needed for the development of  device models and CAD tools that can efficiently describe the device  behavior up to the onset of thermal failure. \u003cbr\u003e  \u003cem\u003eModeling of Electrical Overstress in Integrated Circuits\u003c\/em\u003e is for  VLSI designers and reliability engineers, particularly those who are  working on the development of EOS\/ESD analysis tools. CAD engineers  working on development of circuit level and device level  electrothermal simulators will also benefit from the material covered.  This book will also be of interest to researchers and first and second  year graduate students working in semiconductor devices and IC  reliability fields. \u003cbr\u003e\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 1994-11-30\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9780792395058\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4615-2788-6\u003c\/p\u003e \u003cp\u003eDimensions: 235.0cm x155.0cm\u003c\/p\u003e \u003cp\u003ePages: 148.0\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":45578390634636,"sku":"9780792395058","price":152.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9780792395058.jpg?v=1767145477","url":"https:\/\/lateknightbooks.com\/products\/9780792395058","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}