{"product_id":"9781402070891","title":"The Verilog® Hardware Description Language","description":"\u003ch1\u003eThe Verilog® Hardware Description Language\u003c\/h1\u003e \u003ch2\u003eThomas, Donald E.; Moorby, Philip R.\u003c\/h2\u003e \u003cp\u003exv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment (\"\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2002-06-30\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9781402070891\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/b116662\u003c\/p\u003e \u003cp\u003eDimensions: 235cm x155cm\u003c\/p\u003e \u003cp\u003ePages: 382\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":47667604586636,"sku":"9781402070891","price":116.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9781402070891.jpg?v=1776459794","url":"https:\/\/lateknightbooks.com\/products\/9781402070891","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}