{"product_id":"9781402074455","title":"Low-Voltage CMOS Log Companding Analog Design","description":"\u003ch1\u003eLow-Voltage CMOS Log Companding Analog Design\u003c\/h1\u003e \u003ch2\u003eSerra-Graells, Francisco; Rueda, Adoración; Huertas, José L.\u003c\/h2\u003e \u003cp\u003e\u003cem\u003eLow-Voltage CMOS Log Companding Analog Design\u003c\/em\u003e presents in  detail state-of-the-art analog circuit techniques for the very  low-voltage and low-power design of systems-on-chip in CMOS  technologies. The proposed strategy is mainly based on two bases: the  Instantaneous Log Companding Theory, and the MOSFET operating in the  subthreshold region. The former allows inner compression of the  voltage dynamic-range for very low-voltage operation, while the latter  is compatible with CMOS technologies and suitable for low-power  circuits. The required background on the specific modeling of the MOS  transistor for Companding is supplied at the beginning. Following this  general approach, a complete set of CMOS basic building blocks is  proposed and analyzed for a wide variety of analog signal processing.  In particular, the covered areas include: amplification and AGC,  arbitrary filtering, PTAT generation, and pulse duration modulation  (PDM). For each topic, several case studies areconsidered to  illustrate the design methodology. Also, integrated examples in 1.2um  and 0.35um CMOS technologies are reported to verify the good agreement  between design equations and experimental data. The resulting analog  circuit topologies exhibit very low-voltage (i.e. 1V) and low-power  (few tenths of uA) capabilities. Apart from these specific design  examples, a real industrial application in the field of hearing aids  is also presented as the main demonstrator of all the proposed basic  building blocks. This system-on-chip exhibits true 1V operation, high  flexibility through digital programmability and very low-power  consumption (about 300uA including the Class-D amplifier). As a  result, the reported ASIC can meet the specifications of a complete  family of common hearing aid models. In conclusion, this book is  addressed to both industry ASIC designers who can apply its contents  to the synthesis of very low-power systems-on-chip in standard CMOS  technologies, as wellas to the teachers of modern circuit design in  electronic engineering.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2003-06-30\u003c\/p\u003e \u003cp\u003eFormat: Hardcover\u003c\/p\u003e \u003cp\u003eISBN-13: 9781402074455\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/b105852\u003c\/p\u003e \u003cp\u003eDimensions: 235.0cm x155.0cm\u003c\/p\u003e \u003cp\u003ePages: 192.0\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":45578400825484,"sku":"9781402074455","price":98.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9781402074455.jpg?v=1767145967","url":"https:\/\/lateknightbooks.com\/products\/9781402074455","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}