{"product_id":"9781461285953","title":"From Contamination to Defects, Faults and Yield Loss: Simulation and Applications","description":"\u003ch1\u003eFrom Contamination to Defects, Faults and Yield Loss: Simulation and Applications\u003c\/h1\u003e \u003ch2\u003eKhare, Jitendra B.; Maly, Wojciech\u003c\/h2\u003e \u003cp\u003eOver the years there has been a large increase in the  functionality available on a single integrated circuit. This has been  mainly achieved by a continuous drive towards smaller feature sizes,  larger dies, and better packing efficiency. However, this greater  functionality has also resulted in substantial increases in the  capital investment needed to build fabrication facilities. Given such  a high level of investment, it is critical for IC manufacturers to  reduce manufacturing costs and get a better return on their  investment. The most obvious method of reducing the manufacturing cost  per die is to improve manufacturing yield. \u003cbr\u003e  Modern VLSI research and engineering (which includes design  manufacturing and testing) encompasses a very broad range of  disciplines such as chemistry, physics, material science, circuit  design, mathematics and computer science. Due to this diversity, the  VLSI arena has become fractured into a number of separate sub-domains  with little or no interaction between them. This is the case with the  relationships between testing and manufacturing. \u003cbr\u003e  \u003cem\u003eFrom Contamination to Defects, Faults and Yield Loss: Simulation  and\u003c\/em\u003e \u003cem\u003eApplications\u003c\/em\u003e focuses on the core of the interface between  manufacturing and testing, i.e., the  contamination-defect-fault relationship. The  understanding of this relationship can lead to better solutions of  many manufacturing and testing problems. \u003cbr\u003e  Failure mechanism models are developed and presented which can be used  to accurately estimate probability of different failures for a given  IC. This information is critical in solving key yield-related  applications such as failure analysis, fault modeling and design  manufacturing.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2011-09-26\u003c\/p\u003e \u003cp\u003eFormat: Paperback\u003c\/p\u003e \u003cp\u003e ISBN-10: 9781461285953\u003c\/p\u003e \u003cp\u003eISBN-13: 9781461285953\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4613-1377-9\u003c\/p\u003e \u003cp\u003eDimensions: 235cm x155cm\u003c\/p\u003e \u003cp\u003ePages: 150\u003c\/p\u003e ","brand":"Springer","offers":[{"title":"Default Title","offer_id":44343515447436,"sku":"9781461285953","price":99.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9781461285953_d0af1438-b34d-4205-a638-799fba76fe04.jpg?v=1755056784","url":"https:\/\/lateknightbooks.com\/products\/9781461285953","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}