{"product_id":"9781461346395","title":"A Unified Approach for Timing Verification and Delay Fault Testing","description":"\u003ch1\u003eA Unified Approach for Timing Verification and Delay Fault Testing\u003c\/h1\u003e \u003ch2\u003eSivaraman, Mukund; Strojwas, Andrzej J.\u003c\/h2\u003e \u003cp\u003eLarge system complexities and operation under tight timing  constraints in rapidly shrinking technologies have made it extremely  important to ensure correct temporal behavior of modern-day digital  circuits, both before and after fabrication. Research in  (pre-fabrication) timing verification and (post-fabrication) delay  fault testing has evolved along largely disjoint lines in spite of the  fact that they share many basic concepts. \u003cbr\u003e  \u003cem\u003eA Unified Approach for Timing Verification and Delay Fault  Testing\u003c\/em\u003e applies concepts developed in the context of delay fault  testing to path sensitization, which allows an accurate timing  analysis mechanism to be developed. This path sensitization strategy  is further applied for efficient delay fault diagnosis and delay fault  coverage estimation. \u003cbr\u003e  A new path sensitization strategy called Signal Stabilization Time  Analysis (SSTA) has been developed based on the fact that primitive  PDFs determine the stabilization time of the circuit outputs. This  analysis has been used to develop a feasible method of identifying the  primitive PDFs in a general multi-level logic circuit. An approach to  determine the maximum circuit delay using this primitive PDF  identification mechanism is also presented. The Primitive PDF  Identification-based Timing Analysis (PITA) approach is proved to  determine the maximum floating mode circuit delay exactly under any  component delay model, and provides several advantages over previously  floating mode timing analyzers. \u003cbr\u003e  A framework for the diagnosis of circuit failures caused by  distributed path delay faults is also presented. A metric to quantify  the diagnosability of a path delay fault for a test is also proposed.  Finally, the book presents a very realistic metric for delay fault  coverage which accounts for delay fault size distributions and is  applicable to any delay fault model. \u003cbr\u003e  \u003cem\u003eA Unified Approach for Timing Verification and Delay Fault  Testing\u003c\/em\u003e will be of interest to university and industry researchers  in timing analysis and delay fault testing as well as EDA tool  development engineers and design verification engineers dealing with  timing issues in ULSI circuits. \u003cbr\u003e  The book should also be of interest to digital designers and others  interested in knowing the state of the art in timing verification and  delay fault testing.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2012-09-13\u003c\/p\u003e \u003cp\u003eFormat: Paperback\u003c\/p\u003e \u003cp\u003e ISBN-10: 9781461346395\u003c\/p\u003e \u003cp\u003eISBN-13: 9781461346395\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4419-8578-1\u003c\/p\u003e \u003cp\u003eDimensions: 235cm x155cm\u003c\/p\u003e \u003cp\u003ePages: 155\u003c\/p\u003e ","brand":"Springer","offers":[{"title":"Default Title","offer_id":44358661963916,"sku":"9781461346395","price":99.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9781461346395.jpg?v=1755111456","url":"https:\/\/lateknightbooks.com\/products\/9781461346395","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}