{"product_id":"9781461369486","title":"Loop Tiling for Parallelism","description":"\u003ch1\u003eLoop Tiling for Parallelism\u003c\/h1\u003e \u003ch2\u003eJingling Xue\u003c\/h2\u003e \u003cp\u003eLoop tiling, as one of the most important compiler  optimizations, is beneficial for both parallel machines and  uniprocessors with a memory hierarchy. This book explores the use of  loop tiling for reducing communication cost and improving parallelism  for distributed memory machines. The author provides mathematical  foundations, investigates loop permutability in the framework of  nonsingular loop transformations, discusses the necessary machineries  required, and presents state-of-the-art results for finding  communication- and time-minimal tiling choices. Throughout the book,  theorems and algorithms are illustrated with numerous examples and  diagrams. The techniques presented in \u003cem\u003eLoop Tiling for  Parallelism\u003c\/em\u003e can be adapted to work for a cluster of workstations,  and are also directly applicable to shared-memory machines once the  machines are modeled as BSP (Bulk Synchronous Parallel) machines.  \u003cbr\u003e  Features and key topics: \u003c\/p\u003e\u003cul\u003e \u003cli\u003e Detailed review of the  mathematical foundations, including convex polyhedra and cones; \u003c\/li\u003e  \u003cli\u003e  Self-contained treatment of nonsingular loop transformations, code  generation, and full loop permutability; \u003c\/li\u003e  \u003cli\u003e Tiling loop nests by  rectangles and parallelepipeds, including their mathematical  definition, dependence analysis, legality test, and code generation;  \u003c\/li\u003e  \u003cli\u003e A complete suite of techniques for generating SPMD code for a  tiled loop nest; \u003c\/li\u003e  \u003cli\u003e Up-to-date results on tile size and shape  selection for reducing communication and improving parallelism; \u003c\/li\u003e  \u003cli\u003e  End-of-chapter references for further reading. \u003c\/li\u003e  \u003c\/ul\u003e    Researchers  and practitioners involved in optimizing compilers and students in  advanced computer architecture studies will find this a lucid and  well-presented reference work with numerous citations to original  sources. \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2012-10-12\u003c\/p\u003e \u003cp\u003eFormat: Paperback\u003c\/p\u003e \u003cp\u003eISBN-13: 9781461369486\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-1-4615-4337-4\u003c\/p\u003e \u003cp\u003eDimensions: 235.0cm x155.0cm\u003c\/p\u003e \u003cp\u003ePages: 256.0\u003c\/p\u003e ","brand":"Springer US","offers":[{"title":"Default Title","offer_id":44358968705164,"sku":"9781461369486","price":152.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9781461369486.jpg?v=1767147457","url":"https:\/\/lateknightbooks.com\/products\/9781461369486","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}