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This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.
Published by: Springer
Publication Date: 2011-12-01
Format: Hardcover
ISBN-13: 9781461401308
DOI: 10.1007/978-1-4614-0131-5
Dimensions: 235cm x155cm
Pages: 172