On-Chip Training NPU - Algorithm, Architecture and SoC Design

On-Chip Training NPU - Algorithm, Architecture and SoC Design

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On-Chip Training NPU - Algorithm, Architecture and SoC Design
  • On-Chip Training NPU - Algorithm, Architecture and SoC Design
On-Chip Training NPU - Algorithm, Architecture and SoC Design

On-Chip Training NPU - Algorithm, Architecture and SoC Design

$107.99 $119.99

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On-Chip Training NPU - Algorithm, Architecture and SoC Design

Han, Donghyeon; Yoo, Hoi-Jun

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

Details

Published by: Springer

Publication Date: 2024-07-29

Format: Paperback

ISBN-13: 9783031342394

DOI: 10.1007/978-3-031-34237-0

Dimensions: 235cm x155cm

Pages: 237

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