{"product_id":"9783642646508","title":"VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design","description":"\u003ch1\u003eVLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design\u003c\/h1\u003e \u003ch2\u003eBlinzer, P.; Golze, Ulrich; Cochlovius, E.; Schäfers, M.; Wachsmann, K.-P.\u003c\/h2\u003e \u003cp\u003eThe art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.\u003cbr\u003eAfter emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.\u003c\/p\u003e \u003ch3\u003eDetails\u003c\/h3\u003e \u003cp\u003ePublished by: Springer\u003c\/p\u003e \u003cp\u003ePublication Date: 2014-08-23\u003c\/p\u003e \u003cp\u003eFormat: Paperback\u003c\/p\u003e \u003cp\u003eISBN-13: 9783642646508\u003c\/p\u003e \u003cp\u003eDOI: 10.1007\/978-3-642-61001-1\u003c\/p\u003e \u003cp\u003eDimensions: 235cm x155cm\u003c\/p\u003e \u003cp\u003ePages: 360\u003c\/p\u003e ","brand":"Springer Berlin Heidelberg","offers":[{"title":"Default Title","offer_id":44358742376588,"sku":"9783642646508","price":49.49,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9783642646508.jpg?v=1776523428","url":"https:\/\/lateknightbooks.com\/products\/9783642646508","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}