This book describes digital design techniques with exercises. The concepts and exercises discussed are useful to design digital logic from a set of given specifications.  Looking at current trends of miniaturization, the contents provide practical information on the issues in digital design and various design optimization and performance improvement techniques at logic level. The book explains how to design using digital logic elements and how to improve design performance. The book also covers data and control path design strategies, architecture design strategies, multiple clock domain design and exercises , low-power design strategies and solutions at the architecture and logic-design level. The book covers 60 exercises with solutions and will be useful to engineers during the architecture and logic design phase. The contents of this book prove useful to hardware engineers, logic design engineers, students, professionals and hobbyists looking to learn and usethe digital design techniques during various phases of design.

Vaibbhav Taraate is Entrepreneur and Mentor at "1 Rupee S T". He holds a BE (Electronics) degree from Shivaji University, Kolhapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance)  in 1999 from Indian Institute of Technology (IIT) Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.