{"product_id":"9789813346413","title":"ASIC Design and Synthesis RTL Design Using Verilog","description":"\u003ch1\u003eASIC Design and Synthesis\u003c\/h1\u003e\u003ch2\u003eRTL Design Using Verilog\u003c\/h2\u003e\u003ch3\u003eVaibbhav Taraate\u003c\/h3\u003e\u003cdiv\u003e\u003cb\u003eTechnology \u0026amp; Engineering \/ Electronics \/ Circuits \/ General\u003c\/b\u003e\u003c\/div\u003e\u003cbr\u003e\u003cdiv\u003eThis  book describes simple to complex ASIC design practical scenarios using  Verilog. It builds a story from the basic fundamentals of ASIC designs  to advanced RTL design concepts using Verilog. Looking at current trends of  miniaturization, the contents provide practical information on the  issues in ASIC design and synthesis using Synopsys DC and their  solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs,  low-power design techniques, DFT, pre-layout STA and the overall ASIC  design flow with case studies. The contents of this book will be useful  to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.\u003cbr\u003e\u003cp\u003e\u003c\/p\u003e\n\u003c\/div\u003e\u003cdiv\u003e\n\u003cdiv\u003eVaibbhav  Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E.  (Electronics) degree from Shivaji University, Kolhapur (1995) and  received a Gold Medal for standing first in all engineering branches. He  completed his M.Tech. (Aerospace Control and Guidance) at the Indian  Institute of Technology (IIT) Bombay, India, in 1999. He has over 18  years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog.  He has worked with multinational corporations as a consultant, senior  design engineer, and technical manager. His areas of expertise include  RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization,  static timing analysis, system design using microprocessors, high-speed  VLSI designs, and architecture design of complex SOCs.\u003cbr\u003e\n\u003c\/div\u003e\n\u003cdiv\u003e\n\u003cbr\u003e\u003cbr\u003e\n\u003c\/div\u003e\n\u003cp\u003e\u003c\/p\u003e\n\u003c\/div\u003e\u003cbr\u003e\u003ctable\u003e\n\u003ctr\u003e\n\u003ctd\u003ePublication Date: \u003c\/td\u003e\n\u003ctd\u003e07 January 2021\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePublisher: \u003c\/td\u003e\n\u003ctd\u003eSpringer Nature Singapore\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eImprint: \u003c\/td\u003e\n\u003ctd\u003eSpringer\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eISBN-13: \u003c\/td\u003e\n\u003ctd\u003e9789813346413\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFormat: \u003c\/td\u003e\n\u003ctd\u003eHardback\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePage Count: \u003c\/td\u003e\n\u003ctd\u003e330\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/table\u003e","brand":"Springer Nature Singapore","offers":[{"title":"Default Title","offer_id":53280739917964,"sku":"9789813346413","price":197.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/9545\/1788\/files\/9789813346413.jpg?v=1787239401","url":"https:\/\/lateknightbooks.com\/products\/9789813346413","provider":"Late Knight Books and Services, LLC","version":"1.0","type":"link"}