This book discloses the key points to achieve successful standard cell synthesis, from concept to implementation, that is not found in any other books. Standard cell library is the primitive level in the chip design flow and has significant impact on chip performance and the required time for design closure. However, most books of physical design field introduce standard cell design little. Design section describes the important measure of standard cells such as power performance and area and how to achieve better power performance area in standard cell design. To achieve this, this book starts from basics of transistor characteristics and extend to delay and power of standard cells.

The reader can not only learn the fundamental knowledge and algorithms to make up a standard cell synthesis tool, but also can know the indispensable techniques to realize a practical standard cell synthesis tool that is capable of optimizing the delay, area, pin accessibility, and coupling capacitance of cell layouts. Especially, how to systematically utilize the special M0 layer, which is only available in the nanometer-scale advanced technology nodes and has rarely been systematically discussed how to be applied to cell layout synthesis, is also disclosed in the book.

Yih-Lang Li is Professor of the Department of Computer Science, National Yang Ming Chiao Tung University (NYCU), Hsinchu, Taiwan. Before joining NYCU, he was Associate Manager of Springsoft Corporation. In a standard cell library synthesis project using a commercial FinFET technology node, his team has developed the first cell synthesis tool that can successfully synthesize over 1000 DRC-clean cells with competitive quality to a commercial handcrafted cell library in terms of delay, power, leakage, and area. He has also been serving as Compensation Committee Member and Independent Director of the Board of Directors for AMICCOM Electronics Corporation since 2012. He was Recipient of the Japan Society for the Promotion of Science Faculty Invitation Fellowship. He was Contest Chair of the first CAD contest at ICCAD in 2012 and Technical Program Committee Member for ASP-DAC, ICCAD, and DAC. He was Full Visiting Professor of Kyoto University in 2019.

Shinichi Nishizawa is Assistant Professor of the Graduate School of Information, Product and System, Waseda University. His research target is standard cell library design for the low voltage, low power, and robust operation of VLSI circuit.

Hidetoshi Onodera received B.S., M.S., and Ph.D. degrees in electronic engineering, all from Kyoto University, Kyoto, Japan. He joined the Department of Electronics, Kyoto University, in 1983. He was Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University, till March 2021. He is currently Professor in the Faculty of Informatics, Osaka Gakuin University. His research interests include design technologies for digital, analog, and RF LSIs, with particular emphasis on low-power design, design for manufacturability, and design for dependability. Dr. Onodera served as Program Chair and General Chair of ICCAD and ASP-DAC. He was Chairman of SSCS Kansai Chapter, IEEE CASS Kansai Chapter, IEEE Kansai Section, IPSJ SIG-SLDM (System LSI Design Methodology), and IEICE Technical Group on VLSI Design Technologies. He served as Editor-in-Chief of IEICE Transactions on Electronics and IPSJ Transactions on System LSI Design methodology.